To retrieve information from a magnetic memory array, a sense amplifier typically compares the current flowing through the device under an applied voltage to a reference current. Generally this reference current is generated by applying voltage to a set of reference devices, half of which are set to the high conductance state (“0” or Parallel orientation) and the other half to the low conductance state (“1” or Anti-Parallel orientation). The sense amplifier compares the average current from those reference cells with the current from the device and generates an output signal having a voltage level representing a digital “0” or “1”.
FIG. 1 is a schematic diagram of a magnetic memory array 5. The magnetic memory array has a data magnetic memory sub-array 10 and a reference magnetic memory sub-array 15.
The data magnetic memory sub-array 10 is formed of magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn arranged in rows and columns. Each of the magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn has a magnetic tunnel junction element MTJ and a gating transistor M1 connected serially. A drain of each of the gating transistors M1 is connected to a first terminal of the associated magnetic tunnel junction element MTJ. The source of each of the gating transistors M1 is connected to a ground reference point. The second terminals of the magnetic tunnel junction element MTJ situated on one column are commonly connected to a data bit line DBL0, . . . , DBLn associated with the one column. Each row of the magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn is associated with one word line WL0, WL1, . . . , WLm. The gate of the gating transistors M1 of each of the magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn on each row is connected to the associated word line WL0, WL1, . . . , WLm. The word lines WL0, WL1, . . . , WLm are collectively connected to a word line decode circuit 20. The word line decode circuit 20 selects the row of magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn to be activated for reading or writing and biases the associated word line WL0, WL1, . . . , WLm to activate the gating transistor M1 of the selected magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn.
The data bit lines DBL0, . . . , DBLn that are collectively connected to the columns of the magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn are connected to the bit line biasing and selection circuit 25. The bit line biasing and selection circuit 25 generates the necessary currents and voltages for writing and reading the selected row of magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn. The bit line biasing and selection circuit 25 is connected to a data input of a sense amplifier 35. The sense amplifier 35 compares a read signal for each of the selected magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn of the data bit lines DBL0, . . . , DBLn for determining the data read.
The reference magnetic memory array 15 is formed of at least one set of paired columns of reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm. Each pair of the reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm is connected to one row of the data magnetic memory array 10. The reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm are structurally identical to the data magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn as described above. However, the reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm are programmed such that one column of the reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm are programmed to parallel or “0” state and the reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm of the adjacent column are programmed to anti-parallel or “1” state. The second terminal of the magnetic tunnel junction element MTJ of the reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm on each column are connected to a reference bit line RBL0 and RBL1. The reference bit lines RBL0 and RBL1 are connected to a reference bit line biasing and averaging circuit 35. The reference bit line biasing and averaging circuit 35 provides the necessary biasing current and voltage levels for writing and reading the reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm. Further, the reference bit line biasing and averaging circuit 35 joins the signals of the paired columns of the reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm to average the signals to form a reference signal REF to the sense amplifier 40. FIG. 1 shows a single sense amplifier 40, when in fact, there is multiple sense amplifiers. Each column of the magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn of the data magnetic memory array 10 may have one sense amplifier connected to receive the read signal from is associated column of the magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn. The averaged reference signal REF as applied from the reference bit line biasing and averaging circuit 35 to the sense amplifier 40 is compared in the sense amplifier 40 to the data signal DATA from the selected magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn to determine the data output signal 45 of the magnetic memory array 5.
The read margin is then defined as the signal separation between the data signal DATA and the averaged reference signal REF. In principle, it is desirable to minimize the variations of the averaged reference signal REF so as not to subtract from the read margin. There are three major sources of variations. The first is the sense amplifier 40 variation (one sense amplifier for each column of the magnetic memory cells MC00, . . . MC0n, . . . , MCm0, . . . , MCmn). This variation usually manifests itself as variation in sense amplifier offset. This can be overcome by adjusting offset of each sense amplifier 40 at the time of fabrication and testing. The second source of variation is the contribution from parasitic impedance, such as bit line resistance. This is often overcome by mimicking reference bit lines RBL0 and RBL1 to data bit lines DBL0, . . . , DBLn, and select from multiple of reference devices ones that have similar parasitic impedance and loading as the target devices. The third source of variation is from the variation between reference devices themselves. This variation can be minimized by averaging multiple reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm. This may be accomplished by using more columns of reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm rather than the two shown. The usual minimum of two reference bit lines already reduces this variation by a factor of 1.4. Some system averages four columns of the reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm to double the reduction. Because the variation of the two signal levels of the high conductance state (“0” or Parallel orientation) and to the low conductance state (“1” or Anti-Parallel orientation) is not the same, the optimal reference level is not necessarily midway between parallel orientation and anti-parallel orientation signal levels. To systematically offset reference signal REF, U.S. Pat. No. 8,693,273 (Yuh, et al.) teaches that the reference signal level REF can be adjusted by changing the number of parallel oriented and anti-parallel oriented reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm to systematic shift the reference level.
The methods of using more reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm in parallel or varying the number of parallel oriented and anti-parallel oriented reference magnetic memory cells RCP0, RCAP0, . . . , RCPm, RCAPm aim to produce one optimal consistent reference signal REF relative the device signals. As technology improvements permit smaller scaling of integrated circuit features, both the manufacturing process and the material uniformity induces more circuit variations. When the variations reach a certain level, even a “perfect” reference signal REF is no longer adequate to allow reliably reading data from the magnetic memory array 5.